1. Technical Field
The embodiments described herein relate to a semiconductor circuit technology and, more particularly, to a delay locked loop and a method for controlling the same.
2. Related Art
Generally, a delay locked loop (DLL) is a circuit for synchronizing a phase of an external clock signal, which is supplied from outside of a semiconductor memory device, with a phase of an internal clock signal, which is used within the semiconductor memory device.
Referring to FIG. 1, a conventional delay locked loop circuit includes a differential amplifier 10, a delay line 20, a replica delay 30, a phase detecting unit 40, a control unit 50, and a drive 60.
The delay line 20 includes a coarse delay line 21 and a fine delay line 22. The delay value set up in a unit delayer of the fine delay line 22 is smaller than that set up in a unit delayer of the coarse delay line 21.
The replica delay 30 is a delay circuit for providing a delay time, which is the same as the signal processing time in the semiconductor circuit. The replica delay 30 outputs to the phase detecting unit 40 a feedback clock signal ‘FBCLK’ which is produced by delaying a delay signal ‘MIXOUT’ of the delay line 20 by a predetermined delay time.
The phase detecting unit 40 outputs a phase detection signal ‘POUT’ and a delay mode decision signal ‘COARSE_LOCK’ to the control unit 50, by detecting a phase difference between a reference clock signal outputted from the differential amplifier 10 and the feedback clock signal ‘FBCLK’.
The delay mode decision signal ‘COARSE_LOCK’ is a signal that informs of the completion of the DLL operation using the coarse delay line 21. That is, it is a signal to inform that the time difference between two signals to be delay-locked is smaller than the delay time of the unit delayer in the coarse delay line 21, while the DLL operation is executed by the coarse delay line 21.
The control unit 50 varies the total delay time of the delay line 20 by controlling the coarse delay line 21 or the fine delay line 22 of the delay line 20 according to the phase detection signal ‘POUT’ and the delay mode decision signal ‘COARSE_LOCK’.
The control unit 50 is implemented to control the delay line 20 in two modes. Initially, the DLL operation is carried out by controlling the coarse delay line 21. Thereafter, when the delay mode decision signal ‘COARSE_LOCK’ is activated, the DLL operation is carried out by controlling the fine delay line 22.
The driver 60 outputs a delay locking signal by driving the delay signal ‘MIXOUT’ of the delay line 20.
The DLL operation using the fine delay line 22 is shown in FIG. 2. That is, two output signals ‘FCLK’ and ‘SCLK’ from the coarse delay line 21 are respectively output with a time difference, which corresponds to a half of the delay time in the unit delayer.
The fine delay line 22 carries out the DLL operation in such a manner that the delay time is finely adjusted by making these two signals ‘FCLK’ and ‘SCLK’ different in a mixture rate.
In normal operation environments, when the delay signal ‘MIXOUT’ of the fine delay line 22 has a value that corresponds to a point of (A0), it is assumed that the delay is locked.
Meanwhile, in case that the operational parameters, such as temperature, voltage or operating frequency, are changed, the delay can be locked when the delay signal ‘MIXOUT’ of the fine delay line 22 has a value corresponding to the point of (A1), not at the value corresponding to the point of (A0), due to the phase distortion of the two signals.
However, it takes a lot of time to adjust the delay signal ‘MIXOUT’ of the fine delay line 22 so that the delay signal ‘MIXOUT’ has the value that corresponds to the point of (A1).
As mentioned above, a conventional delay locked loop circuit needs a lot of time to execute the DLL operation using the fine delay line 22 when the operational parameters change. Furthermore, in such circumstances, an error can be caused in the DLL operation because the DLL operation cannot conform to the operating standards of the semiconductor memory device.